One of the major part of the technology of chip-manufacturing that Intel (NASDAQ:INTC) has been sharply focused on for quite a while now is the density and thickness of the transistors, which are considered to be the building blocks when it comes to computer chips. These days Intel (NASDAQ:INTC) and other such companies of the chip producing companies are dealing with an immense increase in wafer cost. This is the reason that they have decided that the way of getting improvement of cost per transistor is to enhance the density at a rate that outpaces the increase in wafer costs.
At present, comparing and contrasting the densities of different construction technologies is exceptionally tricky and problematic, especially as the thickness of a chip is dependent on a lot of things other than the basic assembling procedure i.e. chip-level design choices and targets also perform a substantial part. All things considered, a typical way for chip organizations to analyze process densities is through the least SRAM bitcell sizes that can be assembled with those courses of action.
In one of its exposures back in August, Intel (NASDAQ:INTC) stated that with the size of the SRAM bitcell, it had the capacity to attain with its 14-nanometer methodology was 0.0588um^2. This was, by far, the most reduced reported SRAM bitcell size for a 14/16-nanometer process. This revelation is extremely impressive, but then again, Samsung had reported a high-density SRAM bitcell size of 0.064um^2 and keeping that in mind, it’s not that impressive.
ElectronIQ has recently stated that Samsung’s (NASDAQOTH:SSNLF) 14-nanometer process which is also broadly acclaimed as the densest non-Intel (NASDAQ:INTC) foundry process, offers a high-thickness bitcell size of 0.064um^2 and a superior bitcell size of 0.080um^2. According to a report by the EETimes, Intel (NASDAQ:INTC)’s high-density 14-nanometer bitcell size has a weight of around 0.05um^2, which is a bit less than the 0.0588um^2 bitcell measure that the lower-power variation comes in at.
The high-density bitcell by Intel (NASDAQ:INTC) takes up about 78% of the extent of area of Samsung’s high-density bitcell. The one with low power takes up 73.5% of the area that Samsung’s does. To the extent to which process densities go if these SRAM bitcell sizes are considered, Intel (NASDAQ:INTC)’s 14-nanometer process seems to be the agreeable victor. Although this clash of the processes is positively fascinating and a very much debatable.
It’s critical to remember that assembling methodology is essentially an empowering influence for good processor designs. Intel (NASDAQ:INTC)’s 14-nanometer process will be utilized without a shred of doubt, to great impact in its PC and server offerings because Intel (NASDAQ:INTC)’s design capacities in those business sectors are exceptional and highly regarded as the best, but the question still exists whether it is the best technology or not.
As per guides exhibited at 2014 investor meeting at Intel (NASDAQ:INTC), Intel (NASDAQ:INTC) arrangements were disclosed to reveal its initial 14-nanometer tablet somewhere in 2015 and afterward a top-to-bottom group of 14-nanometer telephone/tablet processors in 2016. In that case, this methodology could lead to a genuine point of interest in mobiles.